Multiplexers and Decoders
Move the select lines and watch the route move — then wire a truth table into the data inputs.
Skip to the animationA multiplexer routes one of many inputs to a single output under the control of a binary select value, and a decoder does the reverse by turning a binary address into exactly one asserted line — between them they are how every datapath and every memory is addressed.
The multiplexer
n select lines choose between 2ⁿ data inputs. Internally a 4-to-1 mux is Y = S₁′S₀′D₀ + S₁′S₀D₁ + S₁S₀′D₂ + S₁S₀D₃ — one AND term per input, all ORed. The unselected inputs are still driven and simply ignored.
It is the hardware equivalent of an array index. Every register-file read port, every ALU result selector and every bus source choice is a multiplexer.
The decoder
A decoder takes an n-bit address and asserts exactly one of 2ⁿ outputs — converting a compact binary number into a one-hot signal. That is what you need whenever something must be selected physically: a memory row, a chip on a bus, a display segment.
Every memory is a decoder driving word lines plus a multiplexer selecting the column, which is why address decoding dominates the area of a memory chip. An enable input matters here: with several decoders sharing a bus, enable lets exactly one drive it while the others go high-impedance.
A mux is also a universal function generator
Put the variables on the select lines and the truth table's output column on the data inputs, and a 2ⁿ-to-1 mux implements any n-variable function with no gates at all. The function has become data.
This is exactly what an FPGA's lookup table is: a large multiplexer whose data inputs come from configuration memory. Loading a bitstream writes truth tables into those cells — the silicon never changes, only the numbers sitting on the mux inputs.
The whole family
| Block | Does | Note |
|---|---|---|
| Multiplexer | many → one | Select a source |
| Demultiplexer | one → many | Route to a destination |
| Decoder | binary → one-hot | Same circuit as a demux, different input naming |
| Encoder | one-hot → binary | Undefined if two inputs are high |
| Priority encoder | many → binary | Reports the highest active input |
A demultiplexer and a decoder are the same hardware — the decoder's enable is the demux's data input. A plain encoder is undefined when two inputs are asserted, so real designs use a priority encoder, which is the basis of interrupt arbitration.
The numbers you will be asked for
- Mux width
n select lines choose 2ⁿ inputs
Two lines, four inputs.
- 4-to-1 mux
Y = Σ (minterm of S) · Dᵢ
One AND term per data input.
- Decoder outputs
2ⁿ outputs, exactly one asserted
One-hot.
- Function generator
any n-variable function needs one 2ⁿ-to-1 mux
The truth table becomes the data inputs.
Advantages and disadvantages
Advantages
- One block handles source selection anywhere in a datapath.
- A decoder converts an address into physical selection with no decisions to make.
- A mux implements any function of its select variables, with no gates.
- The same structure scales from a 2-to-1 selector to an FPGA lookup table.
Disadvantages
- A wide mux is deep and therefore slow; large ones are built as trees.
- Unselected inputs still consume power, since they remain driven.
- A plain encoder is undefined when several inputs are active.
- Using a mux as a function generator costs 2ⁿ data inputs, which grows fast.
Watch it work
Check yourself
question 1 / 4
One question at a time. Pick an answer to see why it is right or wrong, then move on — there is no score to keep and nothing is saved.